The present embodiments relate to memory circuits, and are more particularly directed to such circuits and related systems and methods where, for each memory cell, the wordline bias is used to control the threshold voltage of one or more corresponding cell transistors.
The technology of many modern circuit applications continues to advance at a rapid pace, with one incredibly prolific type of circuit, and one which is highly developed, being digital memory. For such memories, consideration is given to all aspects of design, including maximizing efficiency and increasing performance. These considerations may be further evaluated based on the integrated circuit device in which the memory is formed, where such circuits may be implemented either as stand-alone products, or as part of a larger circuit such as a microprocessor. One often critical factor with respect to digital memories is the tradeoff between current leakage and access speed. Another factor is the cost of the device and this cost is often affected by the overall size and/or layout of the memory architecture. Thus, a desirable memory provides an acceptable level of current leakage and access speed, along with a price which is acceptable given the system or environment in which the memory will be implemented.
In the present state of the art, the tradeoff in memory design between current leakage and access speed may be handled in various ways. For example, it is known that a transistor's threshold voltage affects both its current leakage and the speed with which the transistor conducts. Relatively speaking, a transistor with a high threshold voltage provides a lower current leakage and a slower conduction speed when compared to a transistor with a low threshold voltage. Given these characteristics, one known memory technique is to include transistors in a memory circuit having differing threshold voltages, where transistors performing one function have a first threshold voltage while transistors performing a different function have a second threshold voltage different than the first threshold voltage. For example, one of the functions may involve address receipt and decoding, while another function may be actual access to the information stored by a memory cell. This approach, however, may suffer various drawbacks. For example, even with differing threshold voltages, once a threshold voltage is set for a given transistor, that transistor is still constrained to provide a fixed amount of current leakage and a corresponding conduction speed. Other drawbacks will be ascertainable by one skilled in the art, and may increase device complexity and cost.
By way of further background, U.S. Pat. No. 5,610,533, issued Mar. 11, 1997, and is entitled "Switched Substrate Bias For Logic Circuits" (the '533 Patent). The '533 Patent discloses numerous embodiments, some of which are directed to DRAM memory cells. For these DRAM cells, the '533 Patent proposes altering the threshold voltages of various of the transistors associated with the DRAM. More particularly, switch circuits are disclosed and operate to connect different back biases either directly to the well of a bulk transistor or directly to the body of a silicon-on-insulator (SOI) transistor. In either case, by varying the back bias to the transistors, the threshold voltage of the controlled transistor is controlled to a different level. For example, during a de-activiation period when it is not desired to access the DRAM, the switch circuits increase the threshold voltage of the transistors, thereby reducing current leakage during that period. Conversely, during an activation period when it is desired to access the DRAM, the switch circuits decrease the threshold voltage of the transistors, thereby increasing the conduction speed of the transistor as compared to what it would be if the threshold voltage were left at the level to which it is set during the de-activation period. This approach, however, also may suffer various drawbacks. For example, the '533 Patent discloses controlling all DRAM transistors in the memory array with the same single control circuit(s). Consequently, when the threshold voltage switch occurs, it is applied to all memory cells in the array. During activation, therefore, such an approach may therefore cause leakage in those cells which in fact are not to be accessed by an incoming address. As another drawback, the specific technique of connecting the switch circuits to the controlled transistors is not described in the '533 Patent from a semiconductor layout standpoint and, thus, it is left to one skilled in the art to minimize the vast potential for increasing device size and complexity. As still another example, the switch circuits required to accomplish the threshold voltage changes in the '533 Patent also necessarily increase device size and complexity. As still another example, the '533 Patent is limited to DRAM memories. Still other drawbacks will be ascertainable by one skilled in the art.
Given the above, the preferred embodiments described below further address the aforementioned considerations and drawbacks, and thereby provide a more efficient and desirable integrated circuit configuration.